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Tag: RISC-V

I2C software engineering main function

1. fii_i2c0.c   Related reference articles: RISC-V teaching plan   fii_i2c0.c mainly implements some functions declared in fii_i2c0.h. #include <stdio.h> #include <stdint.h> #include “fii_i2c0.h” #include…

I2C introduction and design

1. Introduction to I2C   Related reference articles: RISC-V teaching plan   PRX100-D develops the EEPROM chip of AT24C02 onboard, and the test of the…

UART software engineering main function

1. fii_uart1.c   Related reference articles: RISC-V teaching plan   fii_uart1.c is mainly used to implement the declared UART1_IRQ_register function in fii_uart1.h #include <stdio.h> #include…

UART introduction and design

1. Introduction to UART   Related reference articles: RISC-V teaching plan Before entering the RISC-V UART interrupt design, here is a brief introduction to the…

PWM engineering code and example waveform

1. Engineering code   Related reference articles: RISC-V teaching plan   The interrupt caused by PWM is also an external interrupt, and its interrupt request…

RISC-V GPIO Interrupt Project Design (2)

2. Engineering code   Related reference articles: RISC-V teaching plan   2.3. fii_gpio.c #include <stdio.h> #include <stdint.h> #include “fii_gpio.h” #include “platform.h” //Function to implement GPIO…

RISC-V GPIO Interrupt Project Design (1)

1. GPIO interrupt source   Related reference articles: RISC-V teaching plan   In PLIC (PLIC introduction click here ), among the external platform-level interrupt sources,…

RISC-V PLIC Project Design(2)

1. PLIC software design   Related reference articles: RISC-V teaching plan   1.4. plic_driver.c #include “platform.h” #include “plic.h” #include “plic_driver.h” #include “encoding.h” #include <string.h> //Initialize…

RISC-V PLIC CPU Design

1. Interrupt source (ID) definition   Related reference articles: RISC-V teaching plan   The definition of the interrupt source on the address map (click here…

RISC-V CSR Registers(2)CSR Registers

1.CSR register   Related reference articles: RISC-V teaching plan   The previous article RISC-V CSR register (1) CSR introduction and CSR instructions briefly introduced the…

RISC-V asm_compile tool uses

In the learning of RISC-V, we provide a method to download the code written by the software personnel to the FPGA development board through the…

load/store Instruction

1. Load-Store Instructions   Related reference articles: RISC-V teaching plan   RV32I is a load-store architecture. Also, only load and store instructions can access memory…

Unconditional Jumps and Conditional Branches

1. Control transfer instruction   Related reference articles: RISC-V teaching plan   There are two main types of control transfer instructions in RV32I: unconditional jumps…

R-Type Integer Register-Register Instructions

1. R-Type integer register-register instruction   Related reference articles: RISC-V teaching plan   The above RISC-V instruction set explanation (3) I-Type shift instruction and U-type…

Device Tree Driver Code Breakdown

This article breaks down and explains the device tree driver code. For related subjects, please refer to the SOC Table of Contents.   First, we…