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RISC-V Syllabus

Reference materials:

RISC-V Reader Chinese

RISC-V User-Level ISA

RISC-V Privileged Architecture

RISC-V Address Map version 1.2

FII-PRX100-D schematics

FII-PRX100-D(ARTIX 100T,XC7A100T) Hardware Reference Guide

  1. Introduction to RISC-V
    1. Introduction to RISC-V(1)Origin of RISC-V
    2. Introduction to RISC-V(2)RISC-V Instruction Set Classification
    3. Introduction to RISC-V(3)RISC-V Processor Prospects and CPU Development in China
    4. Introduction to RISC-V(4)RISC-V Instruction-Length Encoding
  2. RISC-V Instruction Set
    1. RISC-V Instruction Set(1)Unprivileged Integer Register and Instruction Format
    2. RISC-V Instruction Set(2)I-Type Integer Register-Immediate Instructions
    3. RISC-V Instruction Set(3)I-Type Shift Instructions and U-Type Instructions
    4. RISC-V Instruction Set(4)R-Type Integer Register-Register Instructions
    5. RISC-V Instruction Set(5)Unconditional Jumps and Conditional Branches
    6. RISC-V Instruction Set(6)load/store Instruction
    7. RISC-V Instruction Set(7)Instruction Address Align and Addition Overflow
  3. RISC-V Aseenbly Project Design
    1. RISC-V Aseenbly Project Design(1)Flowing LED
    2. RISC-V Aseenbly Project Design(2)RISC-V Assembly Project, asm_run_led
    3. RISC-V Aseenbly Project Design(3)Compile Environment and on-board FPGA Experiemnt
    4. RISC-V Aseenbly Project Design(4)RISC-V Assembly Syntax and ABI
  4. RISC-V CSR Registers
    1. RISC-V CSR Registers(1)Introduction to CSR and CSR Instruction
    2. RISC-V CSR Registers(2)CSR Registers
  5. RISC-V Register File Implementation and Decoder Module
    1. RISC-V Register File Implementation and Decoder Module(1)Classical 5-stage Pipeline
    2. RISC-V Register File Implementation and Decoder Module(2)CPU Modules
    3. RISC-V Register File Implementation and Decoder Module(3)Register File
    4. RISC-V Register File Implementation and Decoder Module(4)Instrcution Decoder
  6. RISC-V ALU and Branch Module
    1. RISC-V ALU and Branch Module(1)ALU Module
    2. RISC-V ALU and Branch Module(2)Branch Module
  7. RISC-V CSR Read and Write Control Module
    1. RISC-V CSR Read and Write Control Module(1)exu_csr Module
    2. RISC-V CSR Read and Write Control Module(2)csr_reg Module
    3. RISC-V CSR Read and Write Control Module(3)CSR Register Implementation 1
    4. RISC-V CSR Read and Write Control Module(4)CSR Register Implementation 2
    5. RISC-V CSR Read and Write Control Module(5)CSR Register Implementation 3
  8. RISC-V LSU,SRAM,GPIO Module
    1. RISC-V LSU,SRAM,GPIO Module(1)exu_lsu Module
    2. RISC-V LSU,SRAM,GPIO Module(2)D_sram Module
    3. RISC-V LSU,SRAM,GPIO Module(3)fii_GPIO Module
  9. RISC-V EXU Module and CPU Excution
    1. RISC-V EXU Module and CPU Excution(1)rv32i_exu Module
    2. RISC-V EXU Module and CPU Excution(2)CPU Excution (Pipeline)
  10. RISC-V Timer Interrupt
    1. RISC-V Timer Interrupt(1)Access Timer Interrupt  Registers
    2. RISC-V Timer Interrupt(2)Timer Interrupt Request
  11. RISC-V Software IDE, Freedom Studio
    1. RISC-V Software IDE, Freedom Studio(1)Freedom Studio Introduction
    2. RISC-V Software IDE, Freedom Studio(2)Create a New C Project
    3. RISC-V Software IDE, Freedom Studio(3)Project Programmer
    4. RISC-V Software IDE, Freedom Studio(4)Project Debugger
  12. RISC-V C Programming 1
    1. RISC-V C Programming 1(1)Introduction to FII-RISC-V CPU and C Project Compilation Process
    2. RISC-V C Programming 1(2)Use Freedom Studio to Create a New Project
    3. RISC-V C Programming 1(3)Linker Script
  13. RISC-V C Programming 2
    1. RISC-V C Programming 2(1)Segment Display Project
    2. RISC-V C Programming 2(2)Button Project
    3. RISC-V C Programming 2(3)Interrupt and Interrupt Projects
  14. RISC-V Bus and Pipeline
    1. RISC-V Bus and Pipeline(1)Introduction to Bus
    2. RISC-V Bus and Pipeline(2)RISC-V CPU Bus Design
    3. RISC-V Bus and Pipeline(3)Introduction to Pipeline
    4. RISC-V Bus and Pipeline(4)RISC-V CPU Pipeline Design
  15. Vivado Simulation project *.coe file Configuration
  16. RISC-V Integrated Toolchain, asm_compile
  17. RISC-V CPU Design Common Problems and Solution 
    1. RISC-V CPU Design Common Problems and Solution(1)
    2. RISC-V CPU Design Common Problems and Solution(2)
  18. RISC-V PLIC Introduction
  19. RISC-V PLIC Design
    1. RISC-V PLIC CPU Design
    2. RISC-V PLIC Project Design(1)
    3. RISC-V PLIC Project Design(2)
  20. RISC-V GPIO Interrupt Project Design
    1. RISC-V GPIO Interrupt Project Design (1)
    2. RISC-V GPIO Interrupt Project Design (2)
  21. PWM Interrupt Project Design
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