1. Load-Store Instructions

 

Related reference articles:

RISC-V teaching plan

 

RV32I is a load-store architecture. Also, only load and store instructions can access memory and peripherals (registers in the CPU can only be manipulated by arithmetic instructions) [1]. The load and store instructions exchange register and memory/peripheral values ​​with each other.

The load instruction is encoded as I-type, and its opcode is 0000_011, and the store instruction is encoded as S-type, and its opcode is 0100_011, as shown in Figure 1.

The effective address is obtained by adding the value in the rs1 register to the sign-extended 12-bit immediate value (the immediate value in the store instruction is split into two parts).

In general, the load instruction copies the value of the effective address in the memory/peripheral to the rd register, and the store instruction copies the value in the rs2 register to the effective address in the memory/peripheral [1].

 

Figure 1 load/store machine encoding format [1]

 

2.LOAD instruction

2.1.LW

The LW(load word) instruction format is LW rd, offset(rs1) . x[rd] = sext( M[x[rs1] + sext(offset)][31:0])

Its machine code is shown in Figure 2, and its funct3 is 010. This instruction reads four bytes (a word, word) from the effective address and writes to the rd register.

Command example:

LW x13, 4(x12)

In the address corresponding to the offset of the number in the x12 register plus 4, read four bytes and store them in the x13 register.

opcode is 000_0011

funct3 is 010

immediate is 12’b0000_0000_0100

rs1 is 5’b0_1100

rd is 5’b0_1101

So the machine code corresponding to LW x13, 4 (x12 ) is 0000_0000_0100_01100_010_01101_0000011, and the corresponding hexadecimal is 32’h0046_2683

Figure 2 LW machine encoding format [2]

 

 

2.2.LH

The LH(load halfword) instruction format is LH rd, offset(rs1) . x[rd] = sext( M[x[rs1] + sext(offset)][15:0])

Its machine code is shown in Figure 3, and its funct3 is 001. This instruction is to read two bytes (halfword, halfword) from the effective address, and write to the rd register after sign bit extension.

Figure 3 LH machine encoding format [2]

 

Command example:

LH x13, 0(x12)

In the corresponding address in the x12 register, two bytes are read out, and after the sign bit is extended, they are stored in the x13 register, as shown in the following figure.

 

 

2.3.LHU

The LHU(load halfword, unsigned) instruction format is LHU rd, offset(rs1) . x[rd] = M[x[rs1] + sext(offset)][15:0]

Its machine code is shown in Figure 4, and its funct3 is 101. This instruction is to read two bytes (halfword, halfword) from the effective address, and write to the rd register after zero extension.

Command example:

LHU x13, 0(x12)

In the corresponding address in the x12 register, two bytes are read out, and after zero extension, they are stored in the x13 register.

Figure 4 LHU machine encoding format [2]

 

2.4.LB

LB (load byte) instruction format is LB rd, offset (rs1) . x[rd] = sext( M[x[rs1] + sext(offset)][7:0])

Its machine code is shown in Figure 5, and its funct3 is 000. This instruction is to read a byte (byte) from the effective address and write it to the rd register after sign bit extension.

Command example:

LB x13, 0(x12)

In the corresponding address in the x12 register, a byte is read out, and after the sign bit is extended, it is stored in the x13 register.

Figure 5 LB machine encoding format [2]

 

2.5.LBU

The LBU(load byte, unsigned) instruction format is LBU rd, offset(rs1) . x[rd] = M[x[rs1] + sext(offset)][7:0]

Its machine code is shown in Figure 6, and its funct3 is 100. This instruction reads a byte (byte) from the effective address and writes it to the rd register after zero-extending.

Command example:

LBU x13, 0(x12)

In the corresponding address in the x12 register, read a byte, after zero-extending, and store it in the x13 register.

Figure 6 LBU machine encoding format [2]

 

3. STORE instruction

3.1.SW

SW (store word) instruction format is SW rs2, offset (rs1) . M[x[rs1] + sext(offset)]= x[rs2][31: 0]

Its machine code is shown in Figure 7, and its funct3 is 010. This instruction stores the four bytes (a word, word) in the rs2 register into the effective address.

Figure 7 SW machine encoding format [2]

Command example:

SW x13, 8(x12)

In the address corresponding to the offset of the number in the x12 register plus 8, store the four bytes in the x13 register, as shown in the following figure.

 

 

3.2.SH

The SH (store halfword) instruction format is SH rs2, offset (rs1) . M[x[rs1] + sext(offset)] = x[rs2][15: 0]

Its machine code is shown in Figure 8, and its funct3 is 001. This instruction stores the lower two bytes (halfword, halfword) of the rs2 register into the effective address.

Command example:

SH x13, 0(x12)

In the corresponding address in the x12 register, store the lower two bytes in the x13 register.

Figure 8 SH machine encoding format [2]

 

3.3.SB

SB (store byte) instruction format is SB rs2, offset (rs1) . M[x[rs1] + sext(offset)]= x[rs2][7: 0]

Its machine code is shown in Figure 9, and its funct3 is 000. This instruction is to store the low-order byte (byte) of the rs2 register into the effective address.

Command example:

SB x13, 0(x12)

In the corresponding address in the x12 register, store the low-order byte in the x13 register.

Figure 9 SB machine encoding format [2]

 

4. Article references

[1]  Riscv.org , 2021. [Online]. Available: https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf. [Accessed: 22- Feb- 2021] .