1.Introduction to CSR
Related reference articles:
RISC-V teaching plan
In addition to the 32 general-purpose registers introduced earlier, there is also a class of extended registers called CSR (control and status register, control and status register). As the name suggests, this type of register is related to controlling the CPU and indicating the state of the CPU.
In addition to CSR instructions, privileged instructions have other privileged instructions. Here, six CSR instructions that operate the CSR register will be introduced.
Some definitions and abbreviations of the specified field behavior in the CSR register are as follows [1]:
- WIRI: Reserved Writes Ignored, Read Ignore Values (Reserved Writes Ignored, Read Ignore Values)
- WPRI: Reserved Writes Preserve Values, Reads Ignore Values
- WLRL: Write/Read Only Legal Values
- WARL: Write Any Values, Reads Legal Values
This is just an introduction, not much discussion.
All CSR instructions can only operate on one CSR register at a time, and its machine code is shown in Figure 1.
It can be seen that the CSR instruction is similar to the I-type instruction. Although there is also a 12-bit immediate field, bits 20-31 of the machine code are actually used to index the address of the corresponding CSR register. So in theory, a total of 2^12 = 4096-bit CSR registers can be implemented.
By convention, the upper bits of the CSR address (CSR[11:8]/bits 31-28 of the machine code) are used to encode the read and write accessibility of the CSR according to the privilege level.
The first two bits (CSR[11:10]/bits 31-30 of machine code) indicate whether this CSR register is readable and writable (00, 01 or 10) or read-only (11).
The next two bits (CSR[9:8]/bits 29-28 of machine code) are encoded to indicate the lowest privilege level [1] that can access this CSR register. 00 => user CSR; 01 => supervisor CSR; 10 => hypervisor CSR; 11 => machine CSR
The opcode of the CSR is 111_0011 and it is called SYSTEM. According to different funct3, different CSR instructions can be determined.
Figure 1 CSR instruction machine code [1]
These six CSR instructions can be divided into two categories:
- One is register operations: CSRRW, CSRRS, CSRRC
- One category is immediate operations: CSRRWI, CSRRSI, CSRRCI. For the 3 instructions of immediate operation, the 5-bit immediate value is placed in the position of rs1, which is called uimm[4:0], because these immediate values are unsigned ( u nsigned imm mediate).
The rd of these 6 CSR instructions is no different from the destination register of general instructions, located in bits 7-11 of the machine code, a total of 5-bit indexes.
Commonly used CSR registers can be divided into 4 groups, namely:
- user mode
- supervisor mode
- Hypervisor mode
- machine mode.
Machine mode is the fundamental, mode that all RISC-V CPUs must implement. The other three are optional. Only the CSR registers in machine mode will be introduced here.
2.CSR instruction
2.1.CSRRW
CSRRW (control and status register read and write, write control status register immediately after reading) instruction format is CSRRW rd, csr, rs1 . t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t
Its machine code is shown in Figure 2, and the funct3 of CSRRW is 001 . This instruction reads and assigns the value in the CSR register to the rd register, and then writes the value in the rs1 register into the CSR register.
for example:
CSRRW x13, mie, x12
Read and assign the value in the mie register to the x13 register, and then write the value in the x12 register into the mie register
It can be seen that its machine code is shown in Figure 2, the CSRRW
opcode is 111_0011
funct3 is 001
The mie register index address is 12’b0011_0000_0100
rs1 is 5’b0_1100
rd is 5’b0_1101
So the machine code corresponding to CSRRW x13, mie, x12 is 0011_0000_0100_01100_001_01101_1110011, and the corresponding hexadecimal is 32’h3046_16f3
Figure 2 CSRRW machine code format [2]
2.2.CSRRS
CSRRS (control and status register read and set, set control status register after reading) instruction format is CSRRS rd, csr, rs1 . t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t
Its machine code is shown in Figure 3, and the funct3 of CSRRS is 010 . This instruction reads and assigns the value in the CSR register to the rd register, and writes the result of bitwise OR (bitwise OR) between the value in the CSR register and the value in the register rs1 into the CSR register.
Command example:
CSRRS x13, mie, x12
Read and assign the value in the mie register to the x13 register, and write the result of bitwise OR of the value in the mie register and the value in the x12 register into the mie register.
Figure 3 CSRRS machine code format [2]
2.3.CSRRC
CSRRC (control and status register read and clear, clear control status register after reading) instruction format is CSRRC rd, csr, rs1 . t = CSRs[csr]; CSRs[csr] = t & ~x[rs1] ; x[rd] = t
Its machine code is shown in Figure 4, and the funct3 of CSRRC is 011. This instruction is to read out the value in the CSR register and assign it to the rd register, and write the result of bitwise AND (bitwise AND) between the value in the CSR register and the value in the register rs1 inversion and write it into the CSR register.
Command example:
CSRRC x13, mie, x12
Read out the value in the mie register and assign it to the x13 register, and write the result of bitwise AND into the mie register after inverting the value in the mie register and the value in the x12 register.
Figure 4 CSRRC machine code format [2]
2.4.CSRRWI
CSRRWI (control and status register read and write immediate, immediate read and write control status register) instruction format is CSRRWI rd, csr, zimm[4:0] . x[rd] = CSRs[csr]; CSRs[csr] = zimm
Here zimm[4:0] represents an immediate value whose high-order bit is extended by 0 (zero). Its machine code is shown in Figure 5, and the funct3 of CSRRWI is 101 . This instruction reads out the value in the CSR register and assigns it to the rd register, and then writes the five-bit zero-extended immediate number zimm into the CSR register.
Command example:
CSRRWI x13, mie, 5
Read out the value in the mie register and assign it to the x13 register, then expand the high bits of 5’b0_0101 to 0 into 32’h0000_0005 and write it into the mie register
Figure 5 CSRRWI machine code format [2]
2.5.CSRRSI
CSRRSI (control and status register read and set immediate, set control status register after immediate data read) instruction format is CSRRSI rd, csr, zimm[4:0] . t = CSRs[csr]; CSRs[csr] = t | zimm; x[rd] = t
Its machine code is shown in Figure 6, and the funct3 of CSRRSI is 110. This instruction reads and assigns the value in the CSR register to the rd register, and writes the value in the CSR register and the five-bit zero-extended immediate value zimm bitwise OR (bitwise OR) result into the CSR register (CSR The fifth and higher bits of the register are unchanged).
Command example:
CSRRSI x13, mie, 5
Read out the value in the mie register and assign it to the x13 register, then extend the high-order bits of 5’b0_0101 to 32’h0000_0005 and write the value in the mie register into the mie register by bitwise OR
Figure 6 CSRRSI machine code format [2]
2.6.CSRRCI
CSRRCI (control and status register read and clear immediate, clear the control status register after immediate data read) instruction format is CSRRCI rd, csr, zimm[4:0] . t = CSRs[csr]; CSRs[csr] = t & ~ zimm; x[rd] = t
Its machine code is shown in Figure 7, and the funct3 of CSRRCI is 111. This instruction reads the value in the CSR register and assigns it to the rd register, and inverts the value in the CSR register and the five-bit zero-extended immediate number zimm, and writes the result of bitwise AND into the CSR. register (the fifth and higher bits of the CSR register are unchanged).
Command example:
CSRRCI x13, mie, 5
Read out the value in the mie register and assign it to the x13 register, then extend the high-order bits of 5’b0_0101 to 0 into 32’h0000_0005, invert it to 32’hFFFF_FFFA and the value in the mie register bitwise AND write it into the mie register
Figure 7 CSRRCI machine code format [2]
3. Article reference
[1] Riscv.org , 2021. [Online]. Available: https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf. [Accessed: 22- Feb- 2021] .
[2] D. Patterson and A. Waterman, The RISC-V reader. Berkeley: Strawberry Canyon LLC, 2018.
