1. Instruction address alignment

Related reference articles:

RISC-V teaching plan

For load/store instructions, the address of the data in memory should be aligned.

• If 32-bit data is accessed, the memory address should be aligned with the 32-bit data, that is, the lowest two bits of D_PC should be 0 (if the memory data is stored in 32-bit units, it means that the data is 4-byte aligned) ;
• If 16-bit data is accessed, the memory address should be aligned with the 16-bit data, and the lowest bit of D_PC should be 0 (indicating that the data is 2-byte aligned);
• If you access 8-bit data, because the unit of memory is a byte, alignment is not required. How to implement it in hardware in CPU design is shown in RISC-V LSU, SRAM, GPIO module (2) The processing of address shift in D_sram module.

Note: RISC-V only supports little-endian format. The comparison between the little-endian format and the big-endian format is shown in Figure 1. If the same 32-bit 0x0A0B0C0D is stored using a different endian, the situation is as shown.

• The highest byte of little-endian is 0x0A, and the lowest byte is 0x0D;
• The most significant byte of big-endian is 0x0D and the least significant byte is 0x0A.

If data is communicated in systems with different endianness, make sure that the data transmitted is in 32-bit units. If data is exchanged in different endian systems in units of one byte, problems may arise. For example, the address (a + 3) corresponding to 0x0A in the little-endian here, in the big-endian system, the data stored in this address is 0x0D.

Figure 1 Big-endian format, little-endian format [1]

RISC-V chose to use little-endian format because of its current commercial dominance. All X86-32 systems and Apple iOS, Google Android OS, and Microsoft Windows for ARM use little-endian address ordering (little-endian) [2].

2. Addition and subtraction overflow handling

The previously mentioned ADD, ADDI and SUB instructions may overflow during calculation. Generally speaking, hardware design ignores arithmetic overflow, so RISC-V relies on software checking. Here’s an example of how addition is handled (subtraction is similar):

• Unsigned addition overflow (assuming x6, x7 are unsigned)
  • ADD x5, x6, x7
  • BLTU x5, x6, overflow (jump to processing branch with the incorrect result)
  • Explanation: x5 is the sum of x6 and x7. If the sum is smaller than the addend, it means that the addition has overflowed, that is, you can go to the branch that handles overflow, overflow
• Add signed numbers, given that imm is a positive number
  • ADDI x5, x6, +imm (positive number)
  • BLT x5, x6, overflow (jumps to processing branches with incorrect results)
  • Explanation: No matter whether x6 is positive or negative, it adds a positive number, and the result should be larger than itself. If a signed comparison of x5 and x6 is performed, x5 is less than x6, indicating that the addition has overflowed, that is, you can go to the branch that handles overflow, overflow
• Except for the above two special cases, for the addition of the general case, the processing is as follows
  • (x7 < 0) && (x6 + x7 >= x6) || (x7 >= 0) && (x6 + x7 < x6)
  • ADD x5, x6, x7
  • SLTI x28, x7, 0
  • SLT x29, x5, x6
  • BNE x28, x29, overflow (jumps to processing branches with incorrect results)
  • explain:
    • If x7 is less than 0, then x28 is 1, then the sum of x6 and x7 should be less than x6, compare x5 and x6, if x5 is less than x6, x29 is 1, if x5 is not less than x6, that means to overflow, at this time x29 is 0. x28 is not equal to x29, i.e. it is possible to go to an incorrect processing branch
    • If x7 is greater than or equal to 0, then x28 is 0, and the sum of x6 and x7 should not be less than x6. Similarly, comparing x5 and x6, if x29 is 1, it means that x5 is less than x6, which means overflow, and x28 is not equal to x29. Go to the incorrect processing branch
  • Or it can be understood as: if (x7 < 0) && (x6 + x7 >= x6) || (x7 >= 0) && (x6 + x7 < x6) then it is an incorrect processing branch

3. Article reference

[1] “Endianness | Wikiwand”, Wikiwand, 2021. [Online]. Available: https://www.wikiwand.com/en/Endianness. [Accessed: 23- Mar- 2021].

[2] D. Patterson and A. Waterman,  The RISC-V reader. Berkeley: Strawberry Canyon LLC, 2018.