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RISC-V teaching plan
The previous article RISC-V CSR register (1) CSR introduction and CSR instructions briefly introduced the CSR register and 6 CSR instructions. This article will introduce some common CSR registers in machine mode.
The table below shows some CSR registers and their corresponding 12-bit addresses.
There are 32 and 64 (128) versions of the mstatus register. The 32-bit version is mainly introduced here. Bits with specific meanings in the mstatus register have special names.
Here we mainly introduce UIE , SIE , MIE bits. These three bits are used for global interrupt enable. When the corresponding bit is 1, the global interrupt is turned on.
- Among them, UIE (user mode interrupt enable) is the user-mode global interrupt enable;
- SIE (supervisor mode interrupt enable) is the global interrupt enable in supervisor mode;
- MIE (machine mode interrupt enable) is the global interrupt enable in machine mode.
When an interrupt occurs, UPIE/SPIE/MPIE will store the value of UIE/SIE/ MIE before entering the interrupt/exception, and the value of UIE/SIE/MIE will be cleared (all interrupts are turned off). The reason for making a two-level interrupt enable stack  is to prepare for supporting interrupt nesting. UPP/SPP/MPP is used to store the value of the privilege mode before entering the interrupt. For example, MPP only supports machine mode, MPP = 2’b11.
Figure 1 32-bit mstatus register
Figure 2 shows the format of the misa register. The highest two bits of MXL [1:0] (machine XLEN, if it is a 32-bit architecture, that is, XLEN is 32) field is used to indicate the CPU architecture when MXL [1:0] is equal to the following value:
- 01 — CPU is 32-bit architecture
- 10 — CPU is 64-bit architecture
- 11 — CPU is 128-bit architecture
Figure 2 misa register
misa bit 0-25 is Extension [25:0] , and the bits 0-25 correspond to 26 letters in English, and also reflect the support of different architectures in RISC-V, as shown in Figure 3. For example, if D of bit 3 is 1, it means that the hardware architecture supports double-precision floating-point extension.
Figure 3 misa Extension 
1.3.mie(machine interrupt enable)
The mie register is mainly used to control the local interrupt mask and is readable and writable. The main bits used are:
- MSIE ( SSIE , USIE ): control software interrupt, 0 — mask interrupt, 1 — open interrupt (machine software interrupt enable)
- MTIE ( STIE , UTIE ): control timer interrupt, 0 — mask interrupt, 1 — open interrupt (machine timer interrupt enable)
- MEIE ( SEIE , UEIE ): control external interrupt, 0 — mask interrupt, 1 — open interrupt (machine external interrupt enable)
Figure 4 mie register
1.4.mip(machine interrupt pending)
The mip register is an interrupt pending register and is only readable. The important bits are:
- MSIP ( SSIP , USIP ): If this bit is set to 1, it means that the software interrupt is in the interrupt pending state (machine software interrupt pending)
- MTIP ( STIP , UTIP ): If this bit is set to 1, it means that the timer interrupt is in the interrupt pending state (machine timer interrupt pending)
- MEIP ( SEIP , UEIP ): If this bit is set to 1, it means that the external interrupt is in the interrupt pending state (machine external interrupt pending)
Figure 5 mip register
The mtvec register is used to store the interrupt or exception entry address. When the system generates an exception or interrupt, the program will jump to the interrupt or exception service subroutine. Its format is shown in Figure 6. The BASE field stores the entry base address (it must be 4-byte aligned, that is to say, the last two bits are 0 by default, and the combination of 30 bits of BASE can represent a 32-bit address). The value of the MODE field represents the entry base address in the form:
- MODE = 2’b00: The entry address of all interrupts or exceptions is determined by BASE
- MODE = 2’b01: Asynchronous interrupt address PC = BASE + 4 X cause (see the description of the mcause register)
Figure 6 mtvec register
Figure 7 shows the structure of the mcause register, and Figure 8 shows the detailed interrupt/exception code explanation. The mcause register records the cause of the latest exception or interrupt event, and serves the interrupt or exception subroutine in the form of exception code. Interrupt indicates that the event is an exception (1’b0) or an interrupt (1’b1). The exception code records the cause of the event.
- If an interrupt is 1, an exception code of 7 indicates an interrupt generated by a machine-mode timer
- When the MODE of the mtvec register is 2’b01, PC = BASE + 4*7.
Figure 7 mcause register
Figure 8 Interrupt/abnormal cause
1.7.mvendorid(machine vendor ID)
The 32-bit read-only JEDEC manufacturer number is stored in the mvendorid register. If there is no commercial implementation for the time being, 0 can be used to return the read value. The encoding format of JEDEC vendor ID is usually composed of continuous byte code and ID byte code, such as 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x8a, by 12 A continuous byte code 0x7f is composed of an ID code 0x8a, and the highest bit of each byte is odd parity. Remove the highest bit (odd parity bit) in the ID, and leave 7 bits and the number of consecutive bytes 0x0C together to form the vendor ID, so the vendor ID is 0x60a.
1.8. Marchid (machine architecture ID)
The marchid register stores the CPU architecture ID, which is only readable. If the read value is 0, it means that the register is not implemented. The combination of mvendorid and marchid defines a microarchitecture that uniquely identifies the implementation.
1.9.mimpid (machine implementation ID)
The mimpid register is also read-only and stores a uniquely identified version of the processor implementation.
1.10.mhartid (machine hart ID)
hart means hardware thread, hardware thread. The mhartid register is 0, indicating that the architecture is a single-core system, and if the hartid is 1, the architecture is a dual-core system.
The full name of mepc is the machine exception program counter, which stores the PC value of the instruction to be executed when an interrupt or exception occurs and will be used as the return address at the end of the abnormal subroutine (mret). This register is readable and writable and is automatically updated when an exception is entered.
The mscratch register is a random read and writes register that can provide temporary variable space for exceptions or interrupt subroutines.
1.13.mcycle, mcycleh (machine cycle counter lower/higher 32 bits)
The mcycle and mcycleh registers together are a 64-bit clock cycle counter, mcycle is the lower 32 bits, and mcycleh is the upper 32 bits. Together they reflect how many clock cycles the processor has executed. Both registers are readable and writable and count automatically in clock cycles.
1.14. minstret, minstreth (machine instructions-retired counter lower/higher 32 bits)
The minstret and minstreth registers together are a 64-bit instruction execution counter, minstret is the lower 32 bits, and minstreth is the upper 32 bits. Together they reflect how many instructions the processor has executed. Both of these registers are readable and writable, and the execution of the instruction triggers automatic counting.
1.15 mtval (machine trap value register)
The mtval register was formerly known as mbadaddr and is a readable and writable register. When an exception is entered, mtval is written with information about the exception to help software handle the exception.
The hardware platform will specify which exceptions must informatively set mtval and which can unconditionally set it to zero. mtval writes to the wrong (virtual) address in the following cases:
- when breakpoint is triggered
- Instruction fetch, load, or store address is misaligned
- When an access page fault exception occurs
When an illegal instruction occurs, mtval can be written to the first faulty instruction. For other traps, mtval is set to zero, but future standards may redefine the mtval setting for other traps.
2. Article reference
 Riscv.org , 2021. [Online]. Available: https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf. [Accessed: 22- Feb- 2021] .