1. Instruction set encoding

Related reference articles:

RISC-V teaching plan

This article will follow the introduction of RISC-V (2) The characteristics and classification of the RISC-V instruction set will introduce the coding structure of the RISC-V instruction set. The instruction length can be divided into 16 bits, 32 bits, 48 ​​bits, 64 bits, 128 bits, etc. according to the instruction encoding, as shown in Figure 1.

1. 16-bit instruction length: The instruction is 16-bit, and the lowest two bits are aa, where aa can be 00, 01, 10 (aa cannot be 11); if aa=11, it must be 32-bit and above.
2. 32-bit instruction length: The instruction is 32-bit, and the lowest five bits are the 32-bit instruction length indication bbbaa, where aa must be 11, bbb is 000-110, and bbb cannot be 111.
3. 48-bit instruction length: The instruction is 48 bits, and the lowest 6 bits are 01_1111. In fact, no manufacturer or individual will support the development of a 48-bit CPU.
4. 64-bit instruction length: The instruction is 64 bits, and the lowest 7 bits are 011_1111.
5. 80-192 bit instruction length: the lowest 7 bits are 111_1111, the 12th-14th are nnn and nnn cannot be 111.
   1. 128-bit instruction length: 128-bit instruction, the lower 7 bits are 111_1111, and the 12-14 bits nnn is 011.
6. Greater than 192-bit instruction length: the lowest 7 bits are 111_1111, and the 12-14th nnn is 111.

Figure 1 RISC-V instruction length encoding [1]

2. Characteristics and advantages of coding structure

The main advantages of the coding structure are as follows:

1. It can quickly identify whether the instruction is 16-bit, 32-bit, 48-bit, 64-bit, or 128-bit, bringing fast and concise identification to the instruction decoder
2. It is convenient for designers to mix and use instruction architectures of different bits, which is convenient for code optimization.
3. The compressed instruction set module (C) has a total of 46 instructions of 16-bit length, but all 46 instructions are not independent but are compressed under special conditions in 32-bit instructions, so each 16-bit instruction can find the 32-bit instruction. Prototype so can be translated into 32-bit instructions by hardware or software before the instructions are decoded. Instruction decoding and execution can still operate as 32-bit instructions. Therefore, if translated into 32-bit instructions before decoding, the compressed format is invisible to a subsequent execution.

3. Instruction set module

1. Standard configuration module

1. 1. RV32I, RV32E: Among them, E is just diversity in I. RV32I defines 32 general-purpose register groups, and RV32E uses 16 of them (register groups will be introduced later).
   2. RV64I
   3. RV128I

2. Extended instruction set, as shown in Figure 2

1. 1. M: Integer Multiplication and Division Instructions
   2. A: Memory atomic (Atomic) operation instructions and Load-Reserved/Store-Conditional instructions
   3. F: Single-precision (32-bit) floating-point instruction set
   4. D: Double-precision (64-bit) floating-point instruction set
   5. C: compressed instruction set, the instruction length is 16 bits

table 1

table 1 Comparison of some extended instruction architectures

4. Article references

[1] D. Patterson and A. Waterman,  The RISC-V reader. Berkeley: Strawberry Canyon LLC, 2018.