FII mainly uses Coremark and Dhrystone as the benchmark test to evaluate the performance of RISC-V3.01 CPU (Central Processing Units, central processing unit) on FII-PRX100-S…
When evaluating hardware, benchmarks are often used to measure the performance of CPUs (Central Processing Units). They are specially designed programs that run a certain…
1.Introduction to Coremark Coremark has been EEMBC’s CPU judging standard since 2009. EEMBC (Embedded Microprocessor Benchmark Consortium, the Embedded Microprocessor Benchmark Consortium) is a…
When we have learned the relevant knowledge of Ethernet and the application of the Ethernet module IP core in the FPGA, we can encapsulate the…
After we have studied the fpga design of the 7-segment nixie tube, we have mastered the display principle of the nixie tube, the realization of…
1. fii_i2c0.c Related reference articles: RISC-V teaching plan fii_i2c0.c mainly implements some functions declared in fii_i2c0.h. #include <stdio.h> #include <stdint.h> #include “fii_i2c0.h” #include…
1. I2C0 module design Related reference articles: RISC-V teaching plan The structure of the RISC-V I2C0 module is shown in Figure 1. Because…
1. Introduction to I2C Related reference articles: RISC-V teaching plan PRX100-D develops the EEPROM chip of AT24C02 onboard, and the test of the…
1. fii_uart1.c Related reference articles: RISC-V teaching plan fii_uart1.c is mainly used to implement the declared UART1_IRQ_register function in fii_uart1.h #include <stdio.h> #include…
1. UART CPU implementation Related reference articles: RISC-V teaching plan The RISC-V UART1 module is the same as the physical layer of the general…
1. Introduction to UART Related reference articles: RISC-V teaching plan Before entering the RISC-V UART interrupt design, here is a brief introduction to the…
1. Engineering code Related reference articles: RISC-V teaching plan The interrupt caused by PWM is also an external interrupt, and its interrupt request…
1. Introduction to PWM Related reference articles: RISC-V teaching plan PWM (pulse-width modulation), pulse width modulation is a method of cutting the electrical…
2. Engineering code Related reference articles: RISC-V teaching plan 2.3. fii_gpio.c #include <stdio.h> #include <stdint.h> #include “fii_gpio.h” #include “platform.h” //Function to implement GPIO…
1. GPIO interrupt source Related reference articles: RISC-V teaching plan In PLIC (PLIC introduction click here ), among the external platform-level interrupt sources,…
1. PLIC software design Related reference articles: RISC-V teaching plan 1.4. plic_driver.c #include “platform.h” #include “plic.h” #include “plic_driver.h” #include “encoding.h” #include <string.h> //Initialize…
1. PLIC software design Related reference articles: RISC-V teaching plan The corresponding PLIC design in the software mainly includes the following modules. …
1. Interrupt source (ID) definition Related reference articles: RISC-V teaching plan The definition of the interrupt source on the address map (click here…
1. Interrupt Related reference articles: RISC-V teaching plan The concept of interruption was introduced in RISC-V C language programming 2 (3) Interrupt and…
1. Pipeline CPU Design Related reference articles: RISC-V teaching plan Based on the previous introduction to the pipeline (click here for the detailed…
1. Introduction to the pipeline Related reference articles: RISC-V teaching plan Before introducing the pipeline, let’s introduce the state machine (Finite-State Machine, FSM).…
1. Learn bus design Learning Design Bus is the learning purpose of this article, follow the design from simple to complex as you learn. This…
This article mainly introduces how to use freedom studio to debug the run_seg project. Related reference articles: RISC-V teaching plan The original block diagram…
This article mainly introduces how to use freedom studio to debug the run_led project. Related reference articles: RISC-V teaching plan 1. Engineering debugging Add…
Related reference articles: RISC-V teaching plan Freedom Studio download project file target board connection First, remove any other USB devices from your computer except the…
This article mainly introduces how to use freedom studio to create a new experimental project from scratch. Related reference articles: RISC-V teaching plan 1. Create…
This article mainly introduces the installation method and basic interface of RISC-V software IDE Related reference articles: RISC-V teaching plan Freedom Studio Brochure (English) 1.…
When using Xilinx Vivado to do simulation projects, sometimes it is necessary to change the initial data of block memory several times quickly. This paper…
In Verilog simulation, the $readmemh system function is sometimes used to help the simulator quickly load the data used for the simulation. In some simple…
1.fii_irq_clint Related reference articles: RISC-V teaching plan After writing into the timer interrupt related register, the module exu_lsu outputs it to the upper…
1. Read the timer interrupt register Related reference articles: RISC-V teaching plan The exu_lsu module was introduced in the RISC-V LSU, SRAM, GPIO…
When the entire RISC-V kernel module is completed, the ITCM module is required to read the machine code of the code written by the software,…
When the entire RISC-V kernel module is completed, the ITCM module is required to read the machine code of the code written by the software,…
The LOAD and STORE instructions in the RISC-V CPU control the SRAM and GPIO modules, SRAM, GPIO, etc., can be regarded as the external storage…
The LOAD and STORE instructions in the RISC-V CPU control the SRAM and GPIO modules, SRAM, GPIO, etc., can be regarded as the external storage…
RISC-V LSU, SRAM, GPIO modules use the LOAD, STORE-related instruction sets in the RISC-V instruction set to access memory or peripheral peripherals. Related reference articles:…
Related reference articles: RISC-V teaching plan This article will complete the last remaining CSR register implementation. For the CSR register implementation that has been…
1. Register module Related reference articles: RISC-V teaching plan The code used in this article is based on FII RISC-V V2.01 (without JTAG and…
The code used in this article is based on FII RISC-V V2.01 (without JTAG and bus). For the upper-level module of csr_reg, see RISC-V CSR…
1. Input/Output Related reference articles: RISC-V teaching plan The code used in this article is based on FII RISC-V V2.01 (without JTAG and…
The BRANCH module of RISC-V is used to handle the conditional jump part of the instruction. This module processes the instructions read by ITCM and…
The ALU module of RISC-V is used to handle the instruction execution part. This module processes the instructions read by ITCM and the relevant information…
In the design of RISC-V FPGA, the core core module of RISC-V includes the instruction decoding module. The main function of this module is to…
In the RISC-V RV32I CPU core, 32 general purpose registers are required. These registers are a critical part of parsing riscv assembly instructions. Related reference…
In the design of RISC-V FPGA, the core framework modules of RISC-V are composed. Related reference articles: RISC-V teaching plan The structure of the…
Classic five-stage pipeline, RISC-V five-stage pipeline In CPU design, pipeline design is often used. Compared with the early state machine logic, pipeline design can effectively…
1.CSR register Related reference articles: RISC-V teaching plan The previous article RISC-V CSR register (1) CSR introduction and CSR instructions briefly introduced the…
1.Introduction to CSR Related reference articles: RISC-V teaching plan In addition to the 32 general-purpose registers introduced earlier, there is also a class…
1. RESET the result before generating the *.bit file First, open the Vivado FII_RISCV_V2.01 project (here, the V2.01 version is used as an example), as…
1. Introduction to assembly language format Related reference articles: RISC-V teaching plan Take asm_run_seg.S as an example: .equ BYTE_DELAY, 0x00100000 .equ GPIO_ADDR, 0xf0000000…