Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2258646
date_generatedFri Aug 6 11:19:42 2021 os_platformWIN64
product_versionVivado v2018.2 (64-bit) project_idcd04606eae9a4e32bd8383eaa0864d01
project_iteration384 random_idf3800b0fa7fc58069541ebe663590231
registration_idf3800b0fa7fc58069541ebe663590231 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagefgg676 target_speed-2
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-8700 CPU @ 3.20GHz cpu_speed3192 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
abstractsearchablepanel_show_search=7 addilaprobespopup_cancel=23 addilaprobespopup_ok=92 addsrcwizard_specify_hdl_netlist_block_design=3
addsrcwizard_specify_or_create_constraint_files=2 addsrcwizard_specify_simulation_specific_hdl_files=4 basedialog_apply=9 basedialog_cancel=615
basedialog_close=7 basedialog_no=2 basedialog_ok=1198 basedialog_yes=30
cfgmempartchooser_density_chooser=4 cfgmempartchooser_manufacturer_chooser=4 cfgmempartchooser_table=3 cfgmempartchooser_type_chooser=4
cfgmempartchooser_width_chooser=4 clockcreationpanel_clock_name=1 clockcreationpanel_enter_positive_number=1 clockgroupscreationpanel_group_name=2
clockgroupspecifierpanel_specify_clocks=3 closeplanner_yes=2 cmdmsgdialog_messages=5 cmdmsgdialog_ok=269
cmdmsgdialog_open_messages_view=1 commandsinput_type_tcl_command_here=41 confirmsavetexteditsdialog_cancel=1 confirmsavetexteditsdialog_no=4
constraintschooserpanel_add_existing_or_create_new_constraints=1 constraintschooserpanel_add_files=2 constraintschooserpanel_create_file=1 coretreetablepanel_core_tree_table=94
createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=4 customizecoredialog_documentation=1 customizeerrordialog_ok=1
debugmenu_remove_from_unassigned_debug_nets=8 debugview_debug_cores_tree_table=15 debugwizard_1_net=2 debugwizard_advanced_trigger=2
debugwizard_capture_control=2 debugwizard_chipscope_tree_table=392 debugwizard_disconnect_all_nets_and_remove_debug=1 debugwizard_find_nets_to_add=29
debugwizard_input_pipe_stages=1 debugwizard_more_info=9 debugwizard_nets=7 debugwizard_only_debug_new_nets=1
debugwizard_remove_nets=121 debugwizard_sample_of_data_depth=34 debugwizard_select_clock_domain=11 debugwizard_this_option_chooses_all_unassigned_debug=21
defaultoptionpane_close=1 editcreateclocktablepanel_edit_create_clock_table=15 editprobeenumsdialog_create_new_enumeration=10 editprobeenumsdialog_table=48
editprobeenumsdialog_value=7 editprobevaluedialog_cancel=3 editprobevaluedialog_ok=1 editsetclockgroupstablepanel_edit_set_clock_groups_table=2
exploreaheadview_reset_selected_runs=463 expreporttreepanel_exp_report_tree_table=2 exprunmenu_make_active=1 expruntreepanel_exp_run_tree_table=488
filesetpanel_file_set_panel_tree=4344 filesetpanel_messages=26 findandpicknetsdialog_nets_tree_table_panel=33 findandreplacealldialog_find=1
floatingtopdialog_select_top_module_of_your_design=1 floatingtopdialog_specify_new_top_module=1 flownavigatortreepanel_flow_navigator_tree=3947 flownavigatorview_collapse_next_level=102
fpgachooser_category=2 fpgachooser_family=4 fpgachooser_fpga_table=6 fpgachooser_package=7
fpgachooser_speed=5 generatedclockcreationpanel_by_clock_edges=3 generatedclockcreationpanel_by_clock_frequency=2 generatedclockcreationpanel_clock_name=1
getobjectsdialog_find=4 getobjectspanel_set=4 graphicalview_zoom_fit=174 graphicalview_zoom_in=97
graphicalview_zoom_out=281 hacgccoefiledialog_close=8 hacgccoefiledialog_save=7 hacgccoefiledialog_validate=1
hacgccoefilewidget_browse=15 hacgccoefilewidget_edit=10 hardwaredashboardoptionspanel_layer_tree=5 hardwaredashboardview_cell_name_for_debug_core=2
hardwareilawaveformview_run_trigger_for_this_ila_core=1115 hardwareilawaveformview_run_trigger_immediate_for_this_ila_core=446 hardwareilawaveformview_stop_trigger_for_this_ila_core=114 hardwareilawaveformview_toggle_auto_re_trigger_mode=60
hardwaretreepanel_hardware_tree_table=953 hcodeeditor_blank_operations=7 hcodeeditor_close=2 hcodeeditor_diff_with=2
hcodeeditor_search_text_combo_box=168 hduallist_find_results=3 hduallist_move_selected_items_to_left=1 hduallist_move_selected_items_to_right=3
hduallist_selected_names=1 hinputhandler_replace_text=1 hinputhandler_toggle_line_comments=22 hjfilechooserrecentlistpreview_recent_directories=87
hpopuptitle_close=4 hstylelistpanel_list_of_style_names=7 ictelementsummarysectionpanel_setup=1 ilaprobetablepanel_add_probe=62
ilaprobetablepanel_add_probes=1 ilaprobetablepanel_remove_selected_probe=51 ilaprobetablepanel_set_trigger_condition_to_global=29 instancemenu_floorplanning=5
intraclockssectionpanel_intra_clocks_section_table=11 labtoolsmenu_name=1 labtoolsmenu_short=1 languagetemplatesdialog_templates_tree=127
mainmenumgr_checkpoint=23 mainmenumgr_design_hubs=5 mainmenumgr_edit=16 mainmenumgr_export=8
mainmenumgr_file=94 mainmenumgr_floorplanning=5 mainmenumgr_flow=10 mainmenumgr_help=2
mainmenumgr_io=3 mainmenumgr_io_planning=5 mainmenumgr_ip=25 mainmenumgr_open_recent_project=13
mainmenumgr_project=53 mainmenumgr_reports=22 mainmenumgr_text_editor=27 mainmenumgr_timing=9
mainmenumgr_tools=116 mainmenumgr_view=8 mainmenumgr_window=16 mainwinmenumgr_layout=12
messagewithoptiondialog_dont_show_this_dialog_again=2 msgtreepanel_discard_user_created_messages=59 msgtreepanel_message_severity=64 msgtreepanel_message_view_tree=504
msgview_critical_warnings=10 msgview_error_messages=2 msgview_information_messages=11 msgview_warning_messages=8
namechooserdialog_name_chooser_list=8 navigabletimingreporttab_timing_report_navigation_tree=33 netlisttreeview_floorplanning=2 netlisttreeview_netlist_tree=38
openfileaction_ok=1 openfileaction_open_directory=1 overwriteconstraintsdialog_overwrite=1 pacodeview_copy=1
pacommandnames_add_config_memory=5 pacommandnames_add_sources=47 pacommandnames_auto_connect_target=127 pacommandnames_auto_update_hier=75
pacommandnames_close_project=5 pacommandnames_close_server=2 pacommandnames_close_target=2 pacommandnames_device_view=1
pacommandnames_draw_pblock_mode=3 pacommandnames_edit_probe_enumeration=4 pacommandnames_fileset_window=1 pacommandnames_generate_composite_file=2
pacommandnames_goto_netlist_design=9 pacommandnames_impl_settings=1 pacommandnames_language_templates=9 pacommandnames_new_file=14
pacommandnames_new_project=3 pacommandnames_open_file=1 pacommandnames_open_hardware_manager=5 pacommandnames_open_project=3
pacommandnames_open_recent_target=1 pacommandnames_open_target_wizard=5 pacommandnames_program_config_memory=7 pacommandnames_program_fpga=461
pacommandnames_refresh_target=1 pacommandnames_replace_in_files=1 pacommandnames_reset_composite_file=2 pacommandnames_reset_run_to_previous_step=1
pacommandnames_resource_utilization=2 pacommandnames_run_bitgen=2 pacommandnames_run_trigger=7 pacommandnames_save_design=146
pacommandnames_save_project_as=8 pacommandnames_schematic=2 pacommandnames_set_as_top=10 pacommandnames_set_global_include=2
pacommandnames_show_product_guide=1 pacommandnames_simulation_live_break=15 pacommandnames_simulation_live_restart=31 pacommandnames_simulation_live_run=36
pacommandnames_simulation_live_run_all=27 pacommandnames_simulation_reset_behavioral=5 pacommandnames_simulation_run_behavioral=71 pacommandnames_simulation_settings=3
pacommandnames_stop_trigger=1 pacommandnames_synth_settings=3 pacommandnames_trigger_immediate=7 pacommandnames_unmark_debug_net=3
pacommandnames_upgrade_ip=3 pacommandnames_verify_device=2 pacommandnames_write_config_memory_file=5 paviews_code=86
paviews_dashboard=78 paviews_device=123 paviews_ip_catalog=6 paviews_path_table=2
paviews_project_summary=3 paviews_schematic=22 paviews_system_monitor=1 paviews_tcl_object_view=11
paviews_timing_constraints=1 pickclockdomainnetdialog_clock_domain_nets_tree=3 planaheadtab_refresh_ip_catalog=2 planaheadtab_show_flow_navigator=1
powerinsttreetablepanel_power_inst_tree_table=4 poweritemtreetablepanel_power_item_tree_table=2 powerresulttab_report_navigation_tree=13 primitivesmenu_highlight_leaf_cells=3
probesview_probes_tree=102 probevaluetablepanel_text_field=146 programcfgmemdialog_contents_of_configuration_file=9 programcfgmemdialog_verify=2
programdebugtab_available_targets_on_server=4 programdebugtab_open_recently_opened_target=16 programdebugtab_open_target=34 programdebugtab_program_device=6
programdebugtab_refresh_device=8 programfpgadialog_program=472 programfpgadialog_specify_bitstream_file=109 programfpgadialog_specify_debug_probes_file=14
programoptionspanelimpl_strategy=2 progressdialog_cancel=3 project_automatic_update_and_compile_order=1 projectnamechooser_choose_project_location=10
projectnamechooser_project_name=10 projectsettingssimulationpanel_tabbed_pane=5 projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=1 projecttab_close_design=4
projecttab_reload=5 rdicommands_copy=13 rdicommands_custom_commands=25 rdicommands_cut=2
rdicommands_delete=46 rdicommands_line_comment=2 rdicommands_properties=16 rdicommands_redo=2
rdicommands_run_script=19 rdicommands_save_file=516 rdicommands_settings=16 rdicommands_undo=66
rdicommands_waveform_save_configuration=18 rdiviews_waveform_viewer=6402 removesourcesdialog_also_delete=5 reportutiltab_report_utilization_navigation_tree=29
rungadget_show_error=4 rungadget_show_error_and_critical_warning_messages=1 saveprojectutils_dont_save=1 saveprojectutils_save=10
sdcgetobjectspanel_specify_clock_source_objects=1 sdcgetobjectspanel_specify_generated_clock_source_objects=1 selectmenu_highlight=7 selectmenu_mark=4
settingsdialog_options_tree=35 settingsdialog_project_tree=17 settingseditorpage_custom_editor=1 settingseditorpage_enter_command_line_for_custom=1
settingseditorpage_use_this_drop_down_list_box_to_select=15 settingsprojectgeneralpage_choose_device_for_your_project=3 settingsprojectippage_cache_scope=2 settingsprojectippage_delete_ip_cache=2
settingsprojectrunpage_choose_report_strategy=2 simpleoutputproductdialog_generate_output_products_immediately=37 simpleoutputproductdialog_reset_output_products=2 simulationliverunforcomp_specify_time_and_units=1
simulationobjectspanel_simulation_objects_tree_table=21 simulationscopespanel_simulate_scope_table=190 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=57 srcchooserpanel_add_or_create_source_file=20
srcchooserpanel_create_file=4 srcchooserpanel_scan_and_add_rtl_include_files_into=1 srcmenu_ip_documentation=5 srcmenu_ip_hierarchy=71
stalerundialog_open_design=14 stalerundialog_yes=4 statemonitor_reset_run=20 syntheticagettingstartedview_recent_projects=41
syntheticastatemonitor_cancel=30 sysmonlegendpanel_selectable_list=2 targetchooserpanel_target_chooser_table=4 taskbanner_close=245
tclconsoleview_clear_all_output=27 tclconsoleview_copy=1 tclconsoleview_tcl_console_code_editor=87 tclfinddialog_display_unique_nets=25
tclobjecttreetable_treetable=201 tclobjectview_add_properties=3 tclobjectview_export_to_spreadsheet=1 tclobjectview_remove_properties_from_main_display=3
tclobjectview_reset_properties=3 timingitemflattablepanel_table=50 timingsumresultstab_show_only_failing_checks=9 topmoduledialog_select_top_module_of_your_design=2
touchpointsurveydialog_no=1 touchpointsurveydialog_remind_me_later=1 touchpointsurveydialog_yes=1 triggercapturecontrolpanel_window_data_depth=7
triggersetuppanel_table=723 triggerstatuspanel_run_trigger_for_this_ila_core=15 triggerstatuspanel_run_trigger_immediate_for_this_ila_core=4 triggerstatuspanel_stop_trigger_for_this_ila_core=1
utilizationhierviewtreetablepanel_table(hierarchy)=4 utilizationinsttreetablepanel_utilization_inst_tree_table(block ram tile)=5 waveformfindbar_close=1 waveformfindbar_find_by=2
waveformnametree_waveform_name_tree=2742 waveformoptionsview_tabbed_pane=2 waveformoptionsview_waveform_options_table=12 waveformview_add=76
waveformview_find=2 waveformview_remove_selected=29 writecfgmemfiledialog_interface=3 writecfgmemfiledialog_load_bitstream_files=4
writecfgmemfiledialog_memory_part=4 writecfgmemfiledialog_overwrite=3 writecfgmemfiledialog_part_chooser=2 writecfgmemfiledialog_specify_bitfile_filename=4
writecfgmemfiledialog_specify_configuration_filename=3 writecfgmemfiledialog_write_checksum=10 xdccategorytree_xdc_category_tree=26 xdctableeditorspanel_create_new_timing_constraint=2
xdcviewertreetablepanel_xdc_viewer_tree_table=14 xpowersettingsdialog_save_these_settings_and_run=1
java_command_handlers
addcfgmem=4 addsources=47 autoconnecttarget=126 closeproject=7
closeserver=2 closetarget=2 coreview=7 customizecore=18
debugwizardcmdhandler=171 editdelete=54 editpaste=2 editprobeenums=4
editproperties=16 editundo=5 fliptoviewtaskimplementation=9 fliptoviewtaskrtlanalysis=1
fliptoviewtasksynthesis=5 launchopentarget=5 launchprogramfpga=477 managecompositetargets=4
newfile=14 newhardwaredashboard=7 newproject=3 opendeviceview=1
openfile=1 openhardwaredashboard=4 openhardwaremanager=143 openproject=3
openrecenttarget=109 programcfgmem=9 programdevice=17 recustomizecore=51
refreshdevice=8 refreshtarget=1 reportclockinteraction=3 reporttimingsummary=1
reportutilization=4 runbitgen=481 runimplementation=13 runpowerestimation=1
runschematic=32 runscript=19 runsynthesis=189 runtrigger=1135
runtriggerimmediate=454 savedesign=146 saveprojectas=8 setglobalinclude=2
setprobenamedisplaytype=1 settopnode=9 showpowerestimation=1 showproductguide=1
showview=98 simulationbreak=15 simulationrestart=31 simulationrun=76
simulationrunall=27 simulationrunfortime=34 stoptrigger=143 tclfind=2
togglecreatepblockmode=3 toolssettings=37 toolstemplates=9 ui.views.c.h.e=1
unmarkdebug=3 upgradeip=3 verifydevice=2 viewlayoutcmd=3
viewtaskimplementation=19 viewtaskprogramanddebug=441 viewtaskprojectmanager=503 viewtaskrtlanalysis=4
viewtasksimulation=13 viewtasksynthesis=13 waveformrenameobject=1 waveformsaveconfiguration=18
writecfgmemfile=5 xdccreateclock=3 xdccreategeneratedclock=1 xdcsetclockgroups=2
xdcsetmulticyclepath=1
other_data
guimode=138
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=35 export_simulation_ies=35
export_simulation_modelsim=35 export_simulation_questa=35 export_simulation_riviera=35 export_simulation_vcs=35
export_simulation_xsim=35 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=75 simulator_language=Mixed srcsetcount=46 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=3 totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=4 carry4=121 fdce=650 fdpe=2
fdre=1476 fdse=13 gnd=58 ibuf=41
ldce=3 lut1=176 lut2=262 lut3=340
lut4=507 lut5=488 lut6=1565 mmcme2_adv=1
muxf7=526 muxf8=128 obuf=2 obuft=40
ramb36e1=4 rams64e=512 vcc=22
pre_unisim_transformation
bufg=4 carry4=121 fdce=650 fdpe=2
fdre=1476 fdse=13 gnd=58 ibuf=2
iobuf=39 ldce=3 lut1=176 lut2=262
lut3=340 lut4=507 lut5=488 lut6=1565
mmcme2_adv=1 muxf7=270 obuf=2 obuft=1
ram256x1s=128 ramb36e1=4 vcc=22

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=4 bram_ports_total=8 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2141 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
blk_mem_gen_v8_4_1/1
c_addra_width=12 c_addrb_width=12 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=4 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 20.285598 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=TDP_RAM_INSTR.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=4096 c_read_depth_b=4096 c_read_width_a=32 c_read_width_b=32
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=0 c_use_byte_wea=0 c_use_byte_web=0
c_use_default_data=1 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=1 c_web_width=1 c_write_depth_a=4096 c_write_depth_b=4096
c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=32 c_write_width_b=32
c_xdevicefamily=artix7 core_container=false iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2018.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=8.4
clk_wiz_v6_0_1_0_0/1
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=SYS_DCM
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=3 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
check-3=1 plio-8=1 reqp-1839=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
lutar-1=2 synth-5=128 timing-18=41 timing-2=1
timing-20=1 timing-9=1 xdcc-1=1 xdcc-7=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.002471 clocks=0.003997
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.097447 die=xc7a100tfgg676-2 dsp_output_toggle=12.500000 dynamic=0.146130
effective_thetaja=2.6 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.019590 input_toggle=12.500000
junction_temp=25.6 (C) logic=0.000671 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.118193 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.243576 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=fgg676 pct_clock_constrained=6.000000 pct_inputs_defined=2
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.001207
simulation_file=None speedgrade=-2 static_prob=False temp_grade=commercial
thetajb=6.8 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=2.6 user_junc_temp=25.6 (C) user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.066251 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.018153 vccaux_total_current=0.084403 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000217 vccbram_static_current=0.000342 vccbram_total_current=0.000559 vccbram_voltage=1.000000
vccint_dynamic_current=0.008465 vccint_static_current=0.015230 vccint_total_current=0.023695 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.005514 vcco33_static_current=0.004000 vcco33_total_current=0.009514 vcco33_voltage=3.300000
version=2018.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=4 block_ram_tile_util_percentage=2.96
ramb18_available=270 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=4 ramb36_fifo_util_percentage=2.96
ramb36e1_only_used=4
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=121
fdce_functional_category=Flop & Latch fdce_used=650 fdpe_functional_category=Flop & Latch fdpe_used=2
fdre_functional_category=Flop & Latch fdre_used=1476 fdse_functional_category=Flop & Latch fdse_used=13
ibuf_functional_category=IO ibuf_used=41 ldce_functional_category=Flop & Latch ldce_used=1
lut1_functional_category=LUT lut1_used=56 lut2_functional_category=LUT lut2_used=310
lut3_functional_category=LUT lut3_used=336 lut4_functional_category=LUT lut4_used=508
lut5_functional_category=LUT lut5_used=455 lut6_functional_category=LUT lut6_used=1477
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=526
muxf8_functional_category=MuxFx muxf8_used=128 obuf_functional_category=IO obuf_used=2
obuft_functional_category=IO obuft_used=40 ramb36e1_functional_category=Block Memory ramb36e1_used=4
rams64e_functional_category=Distributed Memory rams64e_used=512
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=526 f7_muxes_util_percentage=1.66
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=128 f8_muxes_util_percentage=0.81
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=512 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=2760 lut_as_logic_util_percentage=4.35 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=512 lut_as_memory_util_percentage=2.69 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=2141 register_as_flip_flop_util_percentage=1.69
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=1 register_as_latch_util_percentage=<0.01
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=3272 slice_luts_util_percentage=5.16
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=2142 slice_registers_util_percentage=1.69
fully_used_lut_ff_pairs_fixed=1.69 fully_used_lut_ff_pairs_used=57 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=512
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=2760 lut_as_logic_util_percentage=4.35
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=512 lut_as_memory_util_percentage=2.69
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=226
lut_ff_pairs_with_one_unused_lut_output_fixed=226 lut_ff_pairs_with_one_unused_lut_output_used=208 lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=297 lut_flip_flop_pairs_util_percentage=0.47 slice_available=15850 slice_fixed=0
slice_used=1404 slice_util_percentage=8.86 slicel_fixed=0 slicel_used=929
slicem_fixed=0 slicem_used=475 unique_control_sets_used=125 using_o5_and_o6_fixed=125
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=512
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=4336265 bogomips=0 bram18=0 bram36=4
bufg=0 bufr=0 congestion_level=0 ctrls=125
dsp=0 effort=2 estimated_expansions=5082456 ff=2142
global_clocks=3 high_fanout_nets=9 iob=44 lut=3499
movable_instances=6741 nets=7347 pins=40895 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tfgg676-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=fii_cpu_sys -verilog_define=default::[not_specified]
usage
elapsed=00:00:45s hls_ip=0 memory_gain=644.211MB memory_peak=920.629MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::