This article mainly introduces how to use freedom studio to debug the run_led project. Related reference articles: RISC-V teaching plan 1. Engineering debugging Add…
When using Xilinx Vivado to do simulation projects, sometimes it is necessary to change the initial data of block memory several times quickly. This paper…
When the entire RISC-V kernel module is completed, the ITCM module is required to read the machine code of the code written by the software,…
When the entire RISC-V kernel module is completed, the ITCM module is required to read the machine code of the code written by the software,…
The LOAD and STORE instructions in the RISC-V CPU control the SRAM and GPIO modules, SRAM, GPIO, etc., can be regarded as the external storage…
The LOAD and STORE instructions in the RISC-V CPU control the SRAM and GPIO modules, SRAM, GPIO, etc., can be regarded as the external storage…
RISC-V LSU, SRAM, GPIO modules use the LOAD, STORE-related instruction sets in the RISC-V instruction set to access memory or peripheral peripherals. Related reference articles:…
The ALU module of RISC-V is used to handle the instruction execution part. This module processes the instructions read by ITCM and the relevant information…
In the design of RISC-V FPGA, the core core module of RISC-V includes the instruction decoding module. The main function of this module is to…
In the RISC-V RV32I CPU core, 32 general purpose registers are required. These registers are a critical part of parsing riscv assembly instructions. Related reference…
In the design of RISC-V FPGA, the core framework modules of RISC-V are composed. Related reference articles: RISC-V teaching plan The structure of the…
Classic five-stage pipeline, RISC-V five-stage pipeline In CPU design, pipeline design is often used. Compared with the early state machine logic, pipeline design can effectively…
1. RESET the result before generating the *.bit file First, open the Vivado FII_RISCV_V2.01 project (here, the V2.01 version is used as an example), as…
Related reference articles: RISC-V teaching plan Assembly language compiler environment build: After writing the assembler, you can compile it with as.exe to generate the x.bin…
Use RISC-V assembly language to write a led marquee experiment Related reference articles: RISC-V teaching plan # ASSEMBLY PROGRAM DESIGN li x8, 0xf0000000; # set…
In the learning of RISC-V, we provide a method to download the code written by the software personnel to the FPGA development board through the…
Embedded Linux System Basics PetaLinux System Basics Ubuntu Basics – commands and usage Shell Commands and Operands Basic Shell Operations Common Shell Commands APT Download…