RISCV assembly language programming (1) Marquee design

This article mainly introduces the design requirements of the marquee program in assembly language programming, the concept of GPIO, and related hardware knowledge, and prepares for the subsequent analysis of the assembly program.

Related reference articles:

RISC-V teaching plan

 1. The design of the marquee:

Implement the marquee using assembly language.

Program design requirements: Assuming that the system clock is 50Mhz, the state machine version RISC-V CPU executes an instruction about every 3 clock cycles.

Design requirements: There are 8 LEDs in the system (register x10 is used in the assembly language code), in the hardware connection of the RISC-V CPU, we connect LED[7:0] to the outside of group A of RISC-V CPU GPIO peripheral Set register [7:0], shift 1 bit to the right about every 500ms, light up the corresponding LED light, when it moves to the last light (bit 0), then start to shift right from the leftmost end, requiring only one at a time The LED light is on.

    2. Review of knowledge points:

RISC-V general-purpose register part: The CPU has a total of 32 general-purpose registers, and each general-purpose register is 32 bits wide.

Because the LED is designed with a common anode on the development board, the LED lights up when the FPGA pin is low. As shown in the schematic diagram below.

Figure 1. The schematic diagram of the LED circuit of the PRX100T development board

The peripheral address of GPIO is set to 0xF000_0000, of which 0xF000_0000 is the input/output register of IO, and 0xF000_0004 is the direction control register IO_dir[31:0];

• output:

When IO_dir[x] (x=0~31) is 0, the value of the register corresponding to 0xF000_0000 is output to the IO port,

• enter:

When IO_dir[x]=1’b1, when the CPU instruction reads 0xF000_0000, it gets the input outside the IO port.

When IO_dir[x]=1’b0, when the CPU instruction reads 0xF000_0000, the value of the output register is obtained.

PC is a 32-bit wide register, and the corresponding maximum addressing space is 4G. CPU address allocation can refer to the CPU address map file. It includes an introduction to GPIO dedicated addresses.

GPIO (General Purpose Input Output) is a general-purpose input and output pin, which can be used as an input pin or an output pin.

When the direction register is 0 (IO_dir), the 32-bit value saved at address 0xF000_0000 is the output value of the GPIO pin.

Changing the value of 0xF000_0000 is equivalent to changing the value of the GPIO output. Each bit of this value corresponds to the output value of a gpio pin. In theory, one address can control 32 gpio pins, but in fact, only 8 pins can be controlled on the development board, because only 8 pins are reserved for the CPU on the hardware, and only 8 pins are reserved at the 0xf000_0000 address of the CPU. Values ​​in the lower 8 bits are useful.

Notice:

• The x in IO_dir[x] is not the x register mentioned above, but the index number. Indicates that theoretically there can be 32 IOs.
• In theory, we can still read the value of a gpio port in output mode, but because it is in output mode, the value just output will be read.

The concept and structure of FPGA GPIO:

Figure 2. GPIO circuit model

The figure above shows a circuit model of an FPGA GPIO interface. In the middle is a tri-state three-state gate model. Here, the low level of the control pin is valid. When T is 0, the tri-state gate is effectively turned on, and the high level or low level is output from the register and triggered immediately, and GPIO is the output mode. When T is 1, the output terminal is cut off, and IO is in the “Z” high-impedance state. This blocks the output, but the input can be read. The address of the IO location in the CPU is 0xF000_0000, and the address of T is 0xF000_0004, as shown in the figure above. T is the direction control register described above. Assign a value of 1 to the corresponding bit of the address of T to output the gpio port, and assign a value of 0 to the gpio port as an input.

The verification of the program in this design adopts the FII-PRA100-D FPGA and RISC-V development system. For the hardware manual, please refer to the FII-PRX100-D (ARTIX 100T, XC7A100T) hardware reference guide