RISC-V Syllabus

Reference materials：

RISC-V User-Level ISA

RISC-V Privileged Architecture

RISC-V Address Map version

FII-PRX100-D schematics

SiFive Freedom Studio Manual

FII-PRX100-D(ARTIX 100T,XC7A100T) Hardware Reference Guide

FII RISC-V source code V2.01.002

1. Introduction to RISC-V
   1. Introduction to RISC-V（1）Origin of RISC-V
   2. Introduction to RISC-V（2）RISC-V Instruction Set Classification
   3. Introduction to RISC-V（3）RISC-V Processor Prospects and CPU Development in China
   4. Introduction to RISC-V（4）RISC-V Instruction-Length Encoding
2. RISC-V Instruction Set
   1. RISC-V Instruction Set（1）Unprivileged Integer Register and Instruction Format
   2. RISC-V Instruction Set（2）I-Type Integer Register-Immediate Instructions
   3. RISC-V Instruction Set（3）I-Type Shift Instructions and U-Type Instructions
   4. RISC-V Instruction Set（4）R-Type Integer Register-Register Instructions
   5. RISC-V Instruction Set（5）Unconditional Jumps and Conditional Branches
   6. RISC-V Instruction Set（6）load/store Instruction
   7. RISC-V Instruction Set（7）Instruction Address Align and Addition Overflow
3. RISC-V Assembly Project Design
   1. RISC-V asm_compile tool uses
   2. RISC-V Aseenbly Project Design（1）Flowing LED
   3. RISC-V Aseenbly Project Design（2）RISC-V Assembly Project, asm_run_led
   4. RISC-V Aseenbly Project Design（3）Compile Environment and on-board FPGA Experiemnt
   5. RISC-V Aseenbly Project Design（4）RISC-V Assembly Syntax and ABI
   6. FII-PRX100-D development board FPGA programming and RISC-V software code download
4. RISC-V CSR Registers
   1. RISC-V CSR Registers（1）Introduction to CSR and CSR Instruction
   2. RISC-V CSR Registers（2）CSR Registers
5. RISC-V Register File Implementation and Decoder Module
   1. RISC-V Register File Implementation and Decoder Module（1）Classical 5-stage Pipeline
   2. RISC-V Register File Implementation and Decoder Module（2）CPU Modules
   3. RISC-V Register File Implementation and Decoder Module（3）Register File
   4. RISC-V Register File Implementation and Decoder Module（4）Instrcution Decoder
6. RISC-V ALU and Branch Module
   1. RISC-V ALU and Branch Module（1）ALU Module
   2. RISC-V ALU and Branch Module（2）Branch Module
7. RISC-V CSR Read and Write Control Module
   1. RISC-V CSR Read and Write Control Module（1）exu_csr Module
   2. RISC-V CSR Read and Write Control Module（2）csr_reg Module
   3. RISC-V CSR Read and Write Control Module（3）CSR Register Implementation 1
   4. RISC-V CSR Read and Write Control Module（4）CSR Register Implementation 2
   5. RISC-V CSR Read and Write Control Module（5）CSR Register Implementation 3
8. RISC-V LSU，SRAM，GPIO Module
   1. RISC-V LSU，SRAM，GPIO Module（1）exu_lsu Module
   2. RISC-V LSU，SRAM，GPIO Module（2）D_sram Module
   3. RISC-V LSU，SRAM，GPIO Module（3）fii_GPIO Module
9. RISC-V EXU Module and CPU Excution
   1. RISC-V EXU Module and CPU Excution（1）rv32i_exu Module
   2. RISC-V EXU Module and CPU Excution（2）CPU Excution (Pipeline)
10. RISC-V Timer Interrupt
    1. RISC-V Timer Interrupt（1）Access Timer Interrupt  Registers
    2. RISC-V Timer Interrupt（2）Timer Interrupt Request
11. Simulation skills of RISC-V IP core
    1. $readmemh used in Vivado simulation project
    2. Loading of block memory files in vivado simulation projects
12. RISC-V Software IDE, Freedom Studio
    1. RISC-V Software IDE, Freedom Studio（1）Freedom Studio Introduction
    2. RISC-V Software IDE, Freedom Studio（2）Create a New C Project
    3. RISC-V Software IDE, Freedom Studio（3）Project Programmer
    4. RISC-V Software IDE, Freedom Studio（4）run_led Project Debugger
    5. RISC-V Software IDE, Freedom Studio（5）run_led Project Debugger
13. RISC-V C Programming 1
    1. RISC-V C Programming 1（1）Introduction to FII-RISC-V CPU and C Project Compilation Process
    2. RISC-V C Programming 1（2）Use Freedom Studio to Create a New Project
    3. RISC-V C Programming 1（3）Linker Script
14. RISC-V C Programming 2
    1. RISC-V C Programming 2（1）Segment Display Project
    2. RISC-V C Programming 2（2）Button Project
    3. RISC-V C Programming 2（3）Interrupt and Interrupt Projects
15. RISC-V Bus and Pipeline
    1. RISC-V Bus and Pipeline（1）Introduction to Bus
    2. RISC-V Bus and Pipeline（2）RISC-V CPU Bus Design
    3. RISC-V Bus and Pipeline（3）Introduction to Pipeline
    4. RISC-V Bus and Pipeline（4）RISC-V CPU Pipeline Design
16. RISC-V PLIC Design
    1. RISC-V PLIC Introduction
    2. RISC-V PLIC CPU Design
    3. RISC-V PLIC Project Design（1）
    4. RISC-V PLIC Project Design（2）
17. RISC-V GPIO Interrupt Project Design
    1. RISC-V GPIO Interrupt Project Design （1）
    2. RISC-V GPIO Interrupt Project Design （2）
18. RISC-V PWM interrupt design and application
    1. RISC-V PWM interrupt design and application (1) PWM introduction and design
    2. RISC-V PWM interrupt design and application (2) PWM engineering code and example waveform
19. Design and Application of RISC-V UART Interrupt
    1. RISC-V UART interrupt design and application (1) UART introduction and design
    2. RISC-V UART interrupt design and application (2) UART1 CPU implementation and project header file
    3. RISC-V UART interrupt design and application (3) UART software engineering main function
20. RISC-V I2C Interrupt Design and Application
    1. RISC-V I2C interrupt design and application (1) I2C introduction and design
    2. RISC-V I2C interrupt design and application (2) I2C  module CPU implementation and project header file
    3. RISC-V I2C interrupt design and application (3) I2C software engineering main function
21. RISC-V digital tube IP design and application
    1. 7-segment digital tube IP CPU interface package
22. RISC-V Ethernet Design and Application
    1. Ethernet Module Reference
    2. Ethernet module (IP core) RISCV interface package

FII-PRX100-D RISC-V CPU Evaluation

Coremark, Dhrystone package download:

1. FII RISC-V3.01 FII-PRX100-D (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Migration Guide
2. FII RISC-V3.01 FII-PRX100-D (ARTIX-7, XC7A100T) XILINX FPGA Board Dhrystone Migration Guide
3. Performance Evaluation of FII RISC-V3.01 on FII-PRX100-D (ARTIX-7, XC7A100T) XILINX FPGA Board