1. Instruction set architecture
Related reference articles:
RISC-V teaching plan
Instruction Set Architecture (Instruction Set Architecture, ISA) is an abstract model that includes instruction set, registers, memory processing, addressing modes, interrupt and exception handling, and external I/O interfaces. The instruction set includes a series of opcodes, or machine code, and the basic commands that a particular processor executes. ISA specifies the behavior of running machine code on its implementation in a way that is independent of its implementation characteristics. The central processing unit (CPU) can be seen as the implementation of the ISA.
ISA can be classified in many different ways. The most extensive classification is based on the complexity of its architecture, which can be divided into complex instruction set computer (CISC) and reduced instruction set computer (Reduced instruction set computer, RISC). Well-known CISC microprocessors/controllers include Motorola (Motorola) 6800, Intel (Intel) 8080, and X86 series. Architectures based on RISC design include ARM, RISC-V, MIPS, etc. The characteristic of CISC is that it attaches great importance to hardware, including some complex instructions with multiple clock cycles, which is prone to semantic gaps and a small amount of code. The characteristics of RISC are that it tends to attach importance to software, has a simple structure, only includes simplified instructions in a single clock cycle, and has a large amount of code. In general, CISC reduces the number of instructions and sacrifices the clock cycles consumed by each instruction, while RISC greatly reduces the number of cycles per instruction at the cost of multiple instructions. RISC’s strategy brings some very important advantages, namely that single-clock-cycle instructions require less transistor hardware space than CISC, leaving more space for general-purpose registers.
However, the degree of popularization of ISA depends not only on the excellence of the architecture but also on the degree of commercialization. Although RISC has many advantages, due to the lack of software support, the development of RISC chips lags behind CISC. Without commercial interest, many developer companies cannot mass-produce RISC chips, thereby lowering their prices and making them more competitive.
2. The origin of the RISC-V instruction set
The RISC-V architecture is an open-source instruction set invented by Professor Krste Asanovic, Andrew Waterman, and Yunsup Lee of the University of California, Berkeley, USA in 2010, with the help and support of Professor David Patterson, a Turing Award winner. The University of California, Berkeley, is known as the “cradle of electronic engineers” and is a world leader in many electronic engineering research. At that time, when Professor Krste Asanovic was teaching a CPU architecture class, he was swaying between choosing X86 and ARM, hoping to achieve better teaching effects through better choices. However, after in-depth research on existing CPUs on the market, he decided to lead the development of a new architecture himself. In contrast to other ISAs, RISC-V does not require any person or company to pay royalties for designing, producing, and selling chips based on the RISC-V architecture. It has developed to the fifth generation, so it is also called RISC-V (V–five). Due to the release of the draft version of the vector instruction in the same period, V can also be interpreted as Vector.
In May 2017, RISC-V released version 2.22 of the user space instruction set (user space ISA), and the privileged instruction set (privileged ISA) was also in draft version 1.10. Unprivileged instructions were updated on December 13, 2019, Set version 2.2 (that is, the early user space instruction set), privileged instruction set version 1.11, and debug instruction set version 0.13.2. These three versions are the current latest versions.
3. The source of the launch of RISC-V
As mentioned above, the CISC-based X86 series and the RISC-based ARM series are already very mature and extensive in the business, and the CPUs on the market are basically monopolized by ARM and Intel. ARM has been developed in 1985, and Intel X86 has been available since 1978. In this way, RISC-V basically has no chance to develop, but in the end, RISC-V is still popularized, mainly for the following reasons:
- The X86 and ARM architectures have become extremely complex and verbose for backward compatibility. After decades of development, in order to meet the emerging new needs, the original architecture has been modified and expanded many times, which has increased huge costs for learning, use, or maintenance.
- The development and production of X86/ARM chips require high patent and licensing fees, which is very unfriendly to startups. Intel’s CPU architecture in the X86 series is not open at all, and ARM’s IP Core often costs hundreds to tens of millions of upfront license fees (Upfront Licence Fee) and then charges 1-2% of royalties (Royalty Fee) for each chip sold. ).
- X86 and ARM are non-open source systems, and RTL code cannot be obtained or modified. For example, X86 assembly language teaching in colleges and universities usually only teaches software, and it is not meaningful to actually practice and modify its hardware to deepen understanding. At present, ARM has two authorization methods, one is architecture authorization, and the other is “ARM processor IP” license (approximately millions of dollars).
4. Features of RISC-V
RISC-V has two main characteristics:
- As mentioned earlier, the RISC-V ISA is completely open-source, it can be freely used for any purpose, allowing anyone to design, manufacture and sell related chips and software. This feature is the primary reason why RISC-V ISA appears in many American university teaching materials.
- It doesn’t carry the baggage of backward compatibility and overcomes many of the shortcomings of the existing CPU ISA architecture to truly have a late-mover advantage.
Among the CPUs of many RISC ISAs, the reason why RISC-V can stand out is that most RISC CPU designers pay more attention to the design of IP CORE and hardware systems, rather than the creation of an ecological environment. RISC-V not only provides an advanced and efficient instruction system but also established a special foundation to develop and maintain the software ecosystem. The members of the RISC-V foundation include companies such as Google, IBM, Huawei, and Microchip. At present, its headquarters has moved from the United States to Switzerland. . Because ZTE and Huawei were sanctioned by the United States, China has begun to vigorously promote the “independent substitution” of the technology industry, and these alternatives will basically open-source projects, and RISC-V will be one of the promising directions.
5. Article references
[1] https://riscv.org/technical/specifications/
[2] https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/
[3] https://www.wikiwand.com/en/RISC-V
[4] https://riscv.org/members/
[5] https://www.wikiwand.com/en/Complex_instruction_set_computer
[6] https://www.wikiwand.com/en/Reduced_instruction_set_computer
