1. RISC-V instruction set features

Related reference articles:

RISC-V teaching plan

The last article Introduction to RISC-V (1) Origin of RISC-V Describes the background of RISC-V development and compares the importance and advantages of RISC-V with CISC architecture and other RISC architectures simply listed. This article will briefly introduce the characteristics and classification of the instruction set of RISC-V.

In addition to the standard 32-bit RISC-V instruction set, there are 64- and 128-bit architectures. The general-purpose registers of the 64-bit architecture are 64 bits, while the general-purpose registers of the 128-bit architecture are 128 bits, and the corresponding program counters (PC) are also 64 bits and 128 bits, respectively. The powerful 64-bit and 128-bit architectures of the RISC-V instruction set are aimed at mainstream PCs (personal computers), laptops (notebooks), and servers (servers), but have not yet undergone mature commercial development, such as embedded systems. The development of multi-core systems and efficient advanced pipeline systems has made systems based on RISC-V a strong competitor to X86 and ARM systems.

The traditional method of computer architecture is the incremental instruction set. The new processor must not only implement the new instruction set extension but also all the past instruction sets. The purpose is to ensure backward compatibility. Here, X86 and ARM are used. For example:

• X86 has been invented in 1978, and it adds about three instructions per month on average [1]. This means that every newer implementation of X86 must include the previous extension, whether it’s a practical instruction set or a buggy design that no longer makes sense. The downside of this is that the fees that users need to pay keep increasing as the instruction set increases.
• The ARM architecture is divided into three series: A (application), R (real-time), and M (embedded). Each series has been optimized and designed and does not have the function of module combination. The X86 does not have the characteristics of modularity.

The RISC-V instruction set adopts a modular architecture design, which can achieve a balance in terms of cost, power consumption, and performance. The core of RISC-V is:

1) The underlying instruction set of RV32I, is fixed and will never change. This provides stable targets for users and developers.

2) The modularity of the RISC-V instruction set and the combination of modules make it adaptable to different design requirements. For example, if it is to be used as a digital signal processor (DSP), it needs to add a multiplication and division module for data processing, and may not need an atomic instruction set. That is, other modules are optional and will not be a burden to not use, resulting in a bad user experience.

3) The module development of RISC-V will only be for technological reasons, and it will be decided by the foundation. Even if a new module is added, the power to choose to use is still in the hands of the user.

2. RISC-V instruction set classification

RISC-V is divided into subsets such as I, M, E, C, F, D, A, Q, L, B, etc., as shown in Figure 1 (here is the latest version of the instruction subset):

• Basic configuration subset: The basic configuration subset is composed of four types: RV32I, RV32E, RV64I, and RV128I.
• Extended subset: The extended subset is a powerful RISC-V CPU system formed by extending the basic configuration subset. The subset is composed of M, C, F, D, A, Q, L, B, etc.
• The extended subset convention is to be added directly after the base subset name as an indication,
  • For example, add single-precision floating-point extended operations and atomic instructions to RV32I, that is, RV32IFA. RV32I is a 32-bit standard integer instruction set, and it is also the most basic instruction set. It can implement a complete hardware and software system by itself. It is a mandatory part of the instruction set and can adapt to many embedded systems (RV32I).
  • The combined instruction set I, M, A, F, D, C is also called a “general” combination, which is represented by the English letter G (general), that is, RV32G. The RISC-V instruction set can be low power and low cost. Such as the ultra-low-power and ultra-low-cost basic instruction set RV32E, and the standard extended instruction set RV32IC (similar to ARM Thumb), the instruction set can compress the code density to 30%-40%, thereby saving the code space of the memory.

The Version (version number) in Figure 1 is defined by the unprivileged instruction set (ie, the early userspace instruction set) released by RISC-V. The latest version 2.2 was released on December 13, 2019, and you can see the update There are F, D, Q, and other instruction sets that are stopped in the previous version, such as version 2.1. Ratified (approved) and Open (indicating that the development is being drafted) in the Status (status) indicates whether the instruction set is officially released. Frozen means that the module will not have major changes until it is submitted for approval.

Figure 1 RISC-V instruction set (updated on December 13, 2019) [2]

3. Article reference

[1] D. Patterson and A. Waterman,  The RISC-V reader. Berkeley: Strawberry Canyon LLC, 2018.

[2] https://www.wikiwand.com/en/RISC-V#/Design

[3] https://riscv.org/technical/specifications/